ASIC Physical Design Engineer

Pittsburgh, PA, San Francisco Bay Area, or New York City

EngineeringHardware & Silicon

If you are a Physical Design Engineer who wants to impact the transformation of the next evolution of computing, we would like to talk to you. Efficient AI is hiring an ASIC Physical Design Engineer with experience in backend implementation from Netlist to GDSII. We seek individuals to leverage low‑power techniques and design-technology co‑optimization in advanced technology nodes to build energy‑efficient SoCs.

This is a unique opportunity to get in at the ground level and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key responsibilities

  • Take ownership of the physical design of multi-hierarchy low-power designs in advanced technology nodes. This includes executing physical-aware logic synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, IR drop analysis, electromagnetic analysis, and physical verification.
  • Analyze and troubleshoot design and flow issues related to physical design, proactively identifying potential solutions and driving their execution to ensure design PPA target convergence.
  • Take ownership of the integration and/or delivery of IP while effectively highlighting trade-offs between power consumption and performance.
  • Define and implement innovative schemes, such as semi-custom placement and routing techniques, to enhance the performance and power efficiency of Efficient’s IP.
  • Collaborate closely with the digital design team to understand the architecture and provide early feedback on design decisions that relate to physical implementation.
  • Engage with the digital design team to address congestion and timing issues through design modifications and implement functional Engineering Change Orders (ECOs).
  • Implement programming and scripting techniques for EDA tools to automate tasks and enhance the throughput and quality of the physical design process.
  • Engage in effective communication and collaboration with vendors to drive necessary fixes, improvements, and enhancements to Efficient SoC and the design flow.

Minimum qualifications

  • Experience in synthesis, physical design and timing closure.
  • Master's degree in Electrical Engineering with 3+ years of industry experience or PhD in Electrical Engineering with 1+ years of industry experience.
  • In-depth understanding of RTL2GDSII flow and design tape-outs in 22nm or below process technologies.
  • Experience with EDA flow using Cadence/Synopsys/Mentor tools for front‑end (Synthesis/LEC), back‑end (Place and Route), and verification/simulation (Physical Verification).
  • Hands-on experience in SoC floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs.
  • Knowledge of geometry/process/device technology implications on physical design.
  • Experience with hierarchical design implementation and design abstraction techniques.
  • Experience with low power implementation typical in industry, including advanced knowledge of UPF standard (IEEE-1801).
  • Programming and scripting experience in Python, TCL, Verilog/SystemVerilog/VHDL and Bash.

Preferred qualifications

  • Proven track record of design implementation.
  • Experience in full chip floor planning, partitioning, budgeting, and power grid planning.
  • Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.
  • Experience with logic synthesis QoR on low-power designs: transistor flavor selection and corner/cell offer analysis.
  • Definition of design constraints for static timing analysis (synthesis, pre/post‑cts, sign‑off) and corners/voltage definitions.
  • Knowledge of static timing analysis and timing closure constraining, defining timing: constraints and exceptions, corners/voltage definitions.
  • Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology.
  • Experience in validating Power Distribution Networks from package to pg grid, IR/EM: static and dynamic.
  • Experience in integrating analog or mixed-signal macro on top-level design.
  • Experience with Architecture and digital design.

Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, flexibility, and more!  We are committed to personal and professional development and strive to grow together as people and as a company.

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About us

Efficient was established in 2022 as a spinout of Carnegie Mellon University and is currently building a world-class team of hardware and software engineers spanning from silicon implementation to compilers. With seed funding secured, a portfolio of patent-protected IP, and substantial progress on hardware and software development, Efficient is moving quickly toward delivering first silicon in early- to mid-2024.

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Working at Efficient

We are a small, but mighty team, with team members spread across EffHQ in Pittsburgh, Silicon Valley, and New York City. We are a young company on a tremendous growth path. We aim to bring our team together, in-person often and camaraderie is key to our success. We also have the tools and technology to keep us together and interactive as a remote team.

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